VMIVME-4150 is a 12-bit analog output board

The VMIVME-4150 is a 12-bit Analog Output Board which provides 12þisolated high

quality 12-bit analog output channels on a single 6U form factor VMEbus board. Each

channel is electrically isolated from all other channels and from the VMEbus. Listed

below are some features of the VMIVME-4150 :

• 12 fully isolated analog outputs

• 1.000 Vpk isolation, channel-to-channel and channel-to-bus

• 12-bit resolution

• Bipolar voltage output ranges selectable as ±2.5.  ±5.  or ±10 V

• Unipolar voltage output ranges selectable as 0 to 2.5 V, 0 to 5 V, or 0þtoþ10 V

• 10 mA load capacity for voltage outputs over full ±10 V range

• Available with 4 to 20. 0 to 20. or 5 to 25 mA current loop outputs

• 0.05 percent accuracy for voltage outputs, 0.08 percent for current loop outputs

• 4. 8. or 12-channel configurations

• Optical data coupling provides full galvanic isolation

• Static readback data registers simplify program control

• Front panel access for field connections

• Program-controlled connect/disconnect operation of voltage outputs facilitates

system testing

The VMIVME-4150 internal organization is illustrated in the functional block diagram

shown in Figure 1.2-1. The board will operate with sustained isolation voltages as

high as 1.000 Vpk. Bipolar output voltage ranges are  selectable as ±2.5.  ±5.  or ±10þV.

Unipolar output voltage ranges are selectable as 0 to 2.5 V, 0 to 5 V, or 0þtoþ10þV, and

full 10þmA loading is supported throughout these ranges. 4. 8. or 12 channel

configurations are available.

Voltage outputs may be disconnected under program control during system testing,

and are disconnected automatically during reset. Optional current-mode outputs

support applications that require standard 4 to 20. 0 to 20. or 5 to 25 mA analog

current loops. Compliance of the current mode outputs is 9 V if the loop supply

originates on the board, or 27 V with an external loop power supply. A front panel

LED (Fail) is provided. The LED light is on during system reset and can be turned

OFF under user software control.

Optical data coupling, serial data transfers, and isolated D/A converters are used to

produce twelve galvanically isolated analog output channels.  Each channel contains

a serial 12-bit Digital-to-Analog (D/A) converter which generates a signal voltage in

response to commands from the VMEbus.  The D/A converter voltage then drives an

output module which is factory configured for a specific voltage or current output

option.  Power for each channel is supplied as ±15 VDC by an isolated DC/DC

converter.  A functional block diagram of the VMIVME-4150 board is shown in

Figure 1-1 on page 19.

VMIVME-4150

VMEbus Interface

Communications with the VMEbus is controlled with a single Electrically

Programmable Logic Device (EPLD), as shown in Figure 1-1 on page 19.  Data and

control registers are distributed among three Channel-Control EPLD’s.  The control

logic EPLD responds to data transfer requests from the VMEbus, and directs the flow

of data between the bus and the internal data and control registers.  Data Transfer

Acknowledge (DTACK*) is generated when a transfer from the bus has been

completed, or when data is ready to be transferred to the bus.  Transfers proceed

normally if address pipelining is present, but the board will respond only to the first

address in the pipeline sequence.  The VMEbus interface logic will not respond to

transfer requests in which the BERR*, DTACK*, LWORD*, or IACK* control line is

asserted.

Channel Control

Control of data transfer to the output D/A converters is partitioned into three

identical 4-channel groups, with a single EPLD assigned to each group.  This method

of partitioning permits the board to be populated with only those devices required to

support the 4. 8. or 12-channel optional configuration.

As shown in Figure 1-1 on page 19. the EPLD which controls channels 00 through 03

also contains the Board Identification Register (BIR) and part of the Control/Status

register (CSR).  This EPLD detects the presence of one or both of the other two

channel-control EPLD’s, and adjusts the distribution of the CSR accordingly.

Each channel-control EPLD contains four data registers which receive the channel

data words from the VMEbus, and provides an independent data serializer for each

channel.  Figure 1-2 on page 20 illustrates the movement of data within a single

control channel. A data transfer to any 16-bit channel data register from the bus

initiates the serializing process which moves the data to the serial output D/A

converter.  Data in each register is right-justified with 12 significant bits.

Only the 12 significant data bits in each channel are serialized for transfer to the

associated D/A converter.  The three digital signals required to produce the transfer

are shown in Figure 1-3 on page 20. The board selection (BDSEL L) initiates the

transfer sequence.  The CLOCK line provides the primary timing, and clocks the

information present on the DATA line into the serial D/A converter, MSB first

through LSB last.  The output of the converter does not change during the serial

transfer.  When the serial transfer has been completed, the LOAD signal performs a

parallel transfer of data to an output latch in the converter, and the output voltage

responds to the new data.